One or more aspects relate in general to data processing systems, and in particular, to routing communication between computing platforms of a data processing system and external networks.
In recent years the capacity of mainframe class servers has grown, and the quantity of data they are required to handle has grown with them. As a result, the existing prior art computer architectures required modifications to support an order of magnitude increase in the bandwidth. In addition, new Internet applications increased the demand for improved latency. Adapters were needed to support more users and a larger number of connections to consolidate the external network interfaces. The combination of all of the above requirements presented a unique challenge to prior art server I/O subsystems. An enhanced version of an I/O architecture for the mainframe is called queued direct I/O (QDIO). The architecture was initially exploited for Gigabit and Fast Ethernet adapters. More recently the architecture was exploited by the OSA-Express (Open System Architecture-Express) network adapter for Asynchronous Transfer Mode (ATM) and high speed Token Ring connections, and it was exploited by socket network communication for internal virtual machine to virtual machine (logical partition to logical partition) connections. In each of these features, the TCP/IP stack is changed to tightly integrate the new I/O interface and to offload key TCP/IP functions to hardware facilities. For external communications, the offloaded functions are performed by the OSA-Express hardware microcode. The result is a significant improvement in both latency and bandwidth for sockets-based messaging which is transparent to the exploiting applications.
In a multiprocessor environment or a logically partitioned computer as described above, it is often desirable to move data from one processor to another or from one partition to another one. Yet, on an operating system level, it is a significant challenge to develop new network device drivers for each new hardware to be used for communication, as e.g., a TCP/IP communication.
US 2013/0332678 A1, incorporated herein by reference in its entirety, discloses a method for exchanging data with a targeted host using a shared memory communications model. A shared memory communication (SMC) component provides a transparent sockets based communications solution in two variations: a local variation (when the virtual hosts reside on the same physical computing platform having direct access to the same physical memory) by locating a shared memory buffer element in reliance on a connection status bit array; and a remote variation when the virtual servers reside on separate physical computing platforms, by locating a remote memory buffer element in reliance on Remote Direct Memory Access (RDMA) technology. In both variations, the SMC component copies control information to the targeted host's storage. The SMC component updates a targeted logical partition's local producer cursor based on the control information. The SMC component alerts the targeted host indicating data is available to be consumed. The SMC component copies application data to an application receive buffer. The SMC component determines that an application completes a receive operation. The SMC component, updating the targeted logical partition's local consumer cursor to match the targeted logical partition's producer cursor, is responsive to a determination that the application completed the receive operation.